The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8495537 B1

PDF
Full Text
Expired
Date of Patent:
Jul. 23, 2013

Filed:

Jan. 12, 2012
Applicants:

Shyamkumar Thoziyoor, Austin, TX (US);

Tae H. Kim, Chandler, AZ (US);

Sang Y. Lee, Austin, TX (US);

Inventors:

Shyamkumar Thoziyoor, Austin, TX (US);

Tae H. Kim, Chandler, AZ (US);

Sang Y. Lee, Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method, system or computer usable program product for performing timing analysis on an array circuit including receiving in memory a set of pins to be timed, selecting with a data processor a cross section of the array circuit including the set of pins wherein a backtrace is performed from the set of pins to identify a set of bus groups, each bus group having a plurality of timing pins, and assigning timing for an assigned pin of a first bus group equal to timing calculated for a surrogate pin of the first bus group based on array circuit regularity.


Find Patent Forward Citations

Thoziyoor, Shyamkumar. (2013). Timing analysis of an array circuit cross section (U.S. Patent No. 8495537). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8495537

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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