Memory circuitry with write boost and write assist

Abstract

Memory circuitryincludes a memory cellcoupled to a plurality of bit line pairsproviding multiple access ports. Write boost circuitryserves to increase a write voltage applied to write a data value into the memory cell during at least a boost period of a write access. Collision detection circuitrydetects when the write access at least partially overlaps in time with a read access. If a collision is detected, then write assist circuitry serves to drive the bit line pair of the detected read access with a write assist voltage difference having the same polarity as the write voltage and a magnitude less than the write voltage with the boost voltage applied. The write assist circuitry drives the bit line pair of the colliding read independently of the write boost circuitry applying the boost voltage such that the boost voltage is undiminished by the action of the write assist circuitry.