The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 2013

Filed:

Jun. 21, 2011
Applicants:

Mohammed Radwan, Dresden, DE;

Johann Steinmetz, Koenigsbrunn, DE;

Inventors:

Mohammed Radwan, Dresden, DE;

Johann Steinmetz, Koenigsbrunn, DE;

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/311 (2006.01); H01L 21/302 (2006.01); H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

When forming via openings in sophisticated semiconductor devices, a silicon-containing anti-reflective coating (ARC) layer may be efficiently used for adjusting the critical dimension of the via openings by using a two-step etch process in which, in at least one of the process steps, the flow rate of a reactive gas component may be controlled to increase or reduce the resulting width of an opening in the silicon ARC layer. In this manner, the spread of critical dimensions of vias around the target value may be significantly reduced while also reducing any maintenance and rework efforts.


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Radwan, Mohammed. (2013). Method of controlling critical dimensions of vias in a metallization system of a semiconductor device during silicon-arc etch (U.S. Patent No. 8492279). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8492279

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