The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 16, 2013

Filed:

Sep. 28, 2011
Applicants:

Eladio Clemente Delgado, Burnt Hills, NY (US);

Arun Virupaksha Gowda, Rexford, NY (US);

Antonio Caiafa, Albany, NY (US);

Brian Lynn Rowden, Ballston Lake, NY (US);

Ljubisa Dragoljub Stevanovic, Clifton Park, NY (US);

Richard Alfred Beaupre, Pittsfield, MA (US);

Inventors:

Eladio Clemente Delgado, Burnt Hills, NY (US);

Arun Virupaksha Gowda, Rexford, NY (US);

Antonio Caiafa, Albany, NY (US);

Brian Lynn Rowden, Ballston Lake, NY (US);

Ljubisa Dragoljub Stevanovic, Clifton Park, NY (US);

Richard Alfred Beaupre, Pittsfield, MA (US);

Assignee:

General Electric Company, Niskayuna, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/552 (2006.01); H01L 23/34 (2006.01); H01L 23/04 (2006.01); H01L 23/12 (2006.01); H05K 7/20 (2006.01); H05K 9/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A power module includes at least one semiconductor die holding structure. Each die holding structure has a substantially cylindrical outer profile and a central axis. Each die holding structure is disposed within a common cylindrical EMI shield. A plurality of semiconductor devices are mounted to each die holding structure to form a substantially symmetric die mounting pattern respect to the central axis of the die holding structure.


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