The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 16, 2013

Filed:

Jan. 27, 2012
Applicants:

Anil K. Chinthakindi, Wappingers Falls, NY (US);

Timothy J. Dalton, Ridgefield, CT (US);

Ebenezer E. Eshun, Newburgh, NY (US);

Jeffrey P. Gambino, Westford, VT (US);

Anthony K. Stamper, Williston, VT (US);

Kunal Vaed, Poughkeepsie, NY (US);

Inventors:

Anil K. Chinthakindi, Wappingers Falls, NY (US);

Timothy J. Dalton, Ridgefield, CT (US);

Ebenezer E. Eshun, Newburgh, NY (US);

Jeffrey P. Gambino, Westford, VT (US);

Anthony K. Stamper, Williston, VT (US);

Kunal Vaed, Poughkeepsie, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.


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