The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2013

Filed:

Oct. 25, 2011
Applicants:

Xuguang Wang, Eden Prairie, MN (US);

Yong LU, Rosemount, MN (US);

Hai LI, Eden Prairie, MN (US);

Hongyue Liu, Maple Grove, MN (US);

Inventors:

Xuguang Wang, Eden Prairie, MN (US);

Yong Lu, Rosemount, MN (US);

Hai Li, Eden Prairie, MN (US);

Hongyue Liu, Maple Grove, MN (US);

Assignee:

Seagate Technology LLC, Scotts Valley, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 11/14 (2006.01); G11C 11/22 (2006.01); H01L 23/52 (2006.01); H01L 23/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

A memory unit including a first transistor spanning a first transistor region in a first layer of the memory unit; a second transistor spanning a second transistor region in a second layer of the memory unit; a first resistive sense memory (RSM) cell spanning a first memory region in a third layer of the memory unit; and a second RSM cell spanning a second memory region in the third layer of the memory unit, wherein the first transistor is electrically coupled to the first RSM cell, and the second transistor is electrically coupled to the second RSM cell, wherein the second layer is between the first and third layers, wherein the first and second transistor have an transistor overlap region, and wherein the first memory region and the second memory region do not extend beyond the first transistor region and the second transistor region.


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