The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 09, 2013
Filed:
Feb. 09, 2011
Chul-woo Yi, Hwaseong-si, KR;
Seong-jin Jang, Seongnam-si, KR;
Jin-seok Kwak, Hwaseong-si, KR;
Tai-young Ko, Seongnam-si, KR;
Joung-yeal Kim, Yongin-si, KR;
Sang-yun Kim, Hwaseong-si, KR;
Sang-kyun Park, Hwaseong-si, KR;
Jung-bae Lee, Yongin-si, KR;
Chul-woo Yi, Hwaseong-si, KR;
Seong-jin Jang, Seongnam-si, KR;
Jin-seok Kwak, Hwaseong-si, KR;
Tai-young Ko, Seongnam-si, KR;
Joung-yeal Kim, Yongin-si, KR;
Sang-yun Kim, Hwaseong-si, KR;
Sang-kyun Park, Hwaseong-si, KR;
Jung-bae Lee, Yongin-si, KR;
Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;
Abstract
A semiconductor memory device having an open bitline memory structure from which an edge dummy memory block is removed, the semiconductor memory device includes a memory block, an edge sense amplification block including a first sense amplifier having a first bitline, a first complementary bitline, and a first amplification circuit comprising a first transistor having a first size, a central sense amplification block including a second sense amplifier having a second bitline, a second complementary bitline, and a second amplification circuit comprising a second transistor having a second size different from the first size, a capacitor block electrically connected to the edge sense amplification block.