The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 09, 2013
Filed:
Aug. 01, 2012
Philippe Flatresse, Lapierre, FR;
Bastien Giraud, Grenoble, FR;
Jean-philippe Noel, Montbonnot Saint Martin, FR;
Matthieu Le Boulaire, Saint Martin le Vinoux, FR;
Philippe Flatresse, Lapierre, FR;
Bastien Giraud, Grenoble, FR;
Jean-Philippe Noel, Montbonnot Saint Martin, FR;
Matthieu Le Boulaire, Saint Martin le Vinoux, FR;
STMicroelectronics (Crolles 2), Crolles, FR;
Abstract
An IC has cells placed in a cell row having a UTBOX-FDSOI pMOSFET including a ground beneath the pMOS, and an n-doped well beneath it and configured to apply a potential thereto, and a UTBOX-FDSOI nMOSFET including a ground beneath the nMOS, and a p-doped well beneath the ground and configured to apply a potential thereto, and cells, each including a UTBOX-FDSOI pMOSFET including a ground beneath the pMOS, and a p-doped well beneath the ground and configured to apply an electrical potential to the ground, and a UTBOX-FDSOI nMOSFET including a ground beneath the nMOS, and an n-doped well beneath the ground and configured to apply a potential thereto. The cells are placed so that pMOS's of standard cells belonging to a row align along it and a transition cell including a another well and contiguous with first row standard cells thus ensuring continuity with wells of those cells.