The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 02, 2013
Filed:
Mar. 03, 2011
Kaushik DE, Bangalore, IN;
Badri P. Gopalan, Santa Clara, CA (US);
Dhiraj Goswami, Wilsonville, OR (US);
Kaushik De, Bangalore, IN;
Badri P. Gopalan, Santa Clara, CA (US);
Dhiraj Goswami, Wilsonville, OR (US);
Synopsys, Inc., Mountain View, CA (US);
Abstract
An enhanced RTL simulation including information regarding multi-cycle paths is provided. The multi-cycle path information, which is available in the design constraint file, can be used for timing analysis during RTL simulation. This information can advantageously augment the RTL simulation engine to approximate the cycle delays at the destination registers, thereby providing a more realistic approximation of circuit behavior at the RTL level. Notably, RTL simulation is orders of magnitude faster than gate level simulation. Moreover, design bugs associated with multi-cycle paths are more easily corrected during RTL simulation compared to waiting until the gate level simulation.