The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 02, 2013

Filed:

Apr. 16, 2010
Applicants:

Anshuman Chandra, Sunnyvale, CA (US);

Jyotirmoy Saikia, Bangalore, IN;

Rohit Kapur, Cupertino, CA (US);

Inventors:

Anshuman Chandra, Sunnyvale, CA (US);

Jyotirmoy Saikia, Bangalore, IN;

Rohit Kapur, Cupertino, CA (US);

Assignee:

Synopsys, Inc., Mountain View, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

A test architecture adds minimal area overhead and increases encoding bandwidth by using one or more cyclical cache chains for a set of the test patterns provided to the scan chains of the design. A multiplexer associated with a scan chain can be used to bypass a segment of the scan chain that includes unknown values. Blocking circuitry can be programmed to completely block one or more scan chains including unknown values. The test architecture can include control logic for selecting between a linear mode and a cyclical mode. In the linear mode, only top level scan inputs are mapped to the scan chains. In the cyclical mode, outputs of the plurality of cyclical cache chains and top level scan inputs are mapped to the scan chains.


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