The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 02, 2013
Filed:
Jun. 21, 2010
James P. Flynn, Beaverton, OR (US);
Richard H. Steeves, Portland, OR (US);
John T. Stonick, Portland, OR (US);
Daniel K. Weinlader, Allentown, PA (US);
Jianping Wen, Beaverton, OR (US);
Skye Wolfer, Hillsboro, OR (US);
David A. Yokoyama-martin, Portland, OR (US);
Dino A. Toffolon, Stoney Creek, CA;
Jasjeet Singh, Brampton, CA;
James P. Flynn, Beaverton, OR (US);
Richard H. Steeves, Portland, OR (US);
John T. Stonick, Portland, OR (US);
Daniel K. Weinlader, Allentown, PA (US);
Jianping Wen, Beaverton, OR (US);
Skye Wolfer, Hillsboro, OR (US);
David A. Yokoyama-Martin, Portland, OR (US);
Dino A. Toffolon, Stoney Creek, CA;
Jasjeet Singh, Brampton, CA;
Synopsys, Inc., Mountain View, CA (US);
Abstract
One embodiment of the present invention provides a phase-locked loop (PLL) for synthesizing a fractional frequency. The PLL can include a 1/N frequency divider, a voltage-controlled oscillator (VCO), a programmable phase mixer, and a phase detector. The programmable phase mixer can be coupled between an output of the VCO and an input of the frequency divider, wherein the programmable phase mixer is configured to receive the output clock signal from the VCO and generate a first clock signal of frequency fby varying a phase of the output clock signal. The frequency divider is configured to receive the first clock signal from the programmable phase mixer and generate a second clock signal of frequency f=f/N. The phase detector can receive a reference clock signal and the second clock signal as inputs, and the phase detector's output can be used to generate the control voltage for the VCO.