The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 02, 2013
Filed:
Jul. 15, 2010
Hsing-kuo Hsia, Jhubei, TW;
Hung-weng Huang, Hsinchu, TW;
Ching-hua Chiu, Hsinchu, TW;
Gordon Kuo, Taipei, TW;
Hsing-Kuo Hsia, Jhubei, TW;
Hung-Weng Huang, Hsinchu, TW;
Ching-Hua Chiu, Hsinchu, TW;
Gordon Kuo, Taipei, TW;
TSMC Solid State Lighting Ltd., Hsinchu, TW;
Abstract
The present disclosure relates to methods for performing wafer-level measurement and wafer-level binning of LED devices. The present disclosure also relates to methods for reducing thermal resistance of LED devices. The methods include growing epitaxial layers consisting of an n-doped layer, an active layer, and a p-doped layer on a wafer of a growth substrate. The method further includes forming p-contact and n-contact to the p-doped layer and the n-doped layer, respectively. The method further includes performing a wafer-level measurement of the LED by supplying power to the LED through the n-contact and the p-contact. The method further includes dicing the wafer to generate diced LED dies, bonding the diced LED dies to a chip substrate, and removing the growth substrate from the diced LED dies.