The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 25, 2013

Filed:

Jan. 19, 2012
Applicants:

John S. Austin, Winooski, VT (US);

Kai D. Feng, Hopewell Junction, NY (US);

Shiu Chung Ho, Essex Junction, VT (US);

Zhenrong Jin, Essex Junction, VT (US);

Michael R. Ouellette, Westford, VT (US);

Inventors:

John S. Austin, Winooski, VT (US);

Kai D. Feng, Hopewell Junction, NY (US);

Shiu Chung Ho, Essex Junction, VT (US);

Zhenrong Jin, Essex Junction, VT (US);

Michael R. Ouellette, Westford, VT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/38 (2006.01); H03K 19/173 (2006.01);
U.S. Cl.
CPC ...
Abstract

A selectable latch has a pair of parallel pass gates (a first parallel pass gate that receives a seed signal, and a second parallel pass gate that receives a data signal). A first latch logic circuit performs logic operations using signals output by the parallel pass gates to produce an updated data signal. An additional pass gate is operatively connected to the first latch logic circuit. An additional pass gate controls passage of the updated data signal. The output of the parallel pass gates and the additional pass gate is connected to a feedback loop. The feedback loop operates as a dynamic latch for high frequency applications or as a static latch for low frequency applications. Thus, the selectable latch comprises two inputs into the pair of parallel pass gates and performs only one of four logical operations on a received data signal.


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