The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 25, 2013
Filed:
Jul. 21, 2010
Mitsuyoshi Miyazono, Tokyo, JP;
Shigekazu Komatsu, Nirasaki, JP;
Dai Shinozaki, Nirasaki, JP;
Masahiro Kato, Matsumoto, JP;
Atsushi Yoshida, Matsumoto, JP;
Mitsuyoshi Miyazono, Tokyo, JP;
Shigekazu Komatsu, Nirasaki, JP;
Dai Shinozaki, Nirasaki, JP;
Masahiro Kato, Matsumoto, JP;
Atsushi Yoshida, Matsumoto, JP;
Tokyo Electron Limited, Tokyo, JP;
Fuji Electric Systems Co., Ltd., Tokyo, JP;
Abstract
A yield and productivity of a semiconductor module are improved. A sheet having electrical conductivity is fixed to a main surface of a semiconductor substrate on which a plurality of semiconductor devices having a surface structure and a rear surface electrode are arranged. The semiconductor substrate is divided into semiconductor chips on a first support stage in the state where the sheet is fixed to its main surface. The plurality of divided semiconductor chips are mounted on a second support stage via the sheet and further, the plurality of mounted semiconductor chips are continuously subjected to a dynamic characteristic test on the second support stage. The proposed semiconductor device evaluation method permits a fissure growing and propagating from a crack occurring in the dynamic characteristic test of the vertical semiconductor devices to be suppressed, and the yield and productivity of the semiconductor module to be improved.