The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 25, 2013
Filed:
Jul. 28, 2011
Kerry Bernstein, Underhill, VT (US);
Timothy Dalton, Ridgefield, CT (US);
Jeffrey Peter Gambino, Westford, VT (US);
Mark David Jaffe, Shelburne, VT (US);
Paul David Kartschoke, Williston, VT (US);
Stephen Ellinwood Luce, Underhill, VT (US);
Anthony Kendall Stamper, Williston, VT (US);
Kerry Bernstein, Underhill, VT (US);
Timothy Dalton, Ridgefield, CT (US);
Jeffrey Peter Gambino, Westford, VT (US);
Mark David Jaffe, Shelburne, VT (US);
Paul David Kartschoke, Williston, VT (US);
Stephen Ellinwood Luce, Underhill, VT (US);
Anthony Kendall Stamper, Williston, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A double-sided integrated circuit chips, methods of fabricating the double-sided integrated circuit chips and design structures for double-sided integrated circuit chips. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.