The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 25, 2013
Filed:
Nov. 02, 2011
Applicants:
Weize Xiong, Plano, TX (US);
Deborah J. Riley, Murphy, TX (US);
Inventors:
Weize Xiong, Plano, TX (US);
Deborah J. Riley, Murphy, TX (US);
Assignee:
Texas Instruments Incorporated, Dallas, TX (US);
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01);
U.S. Cl.
CPC ...
Abstract
A process for forming an integrated circuit with reduced sidewall spacers to enable improved silicide formation between minimum spaced transistor gates. A process for forming an integrated circuit with reduced sidewall spacers by first forming sidewall spacer by etching a sidewall dielectric and stopping on an etch stop layer, implanting source and drain dopants self aligned to the sidewall spacers, followed by removing a portion of the sidewall dielectric and removing the etch stop layer self aligned to the reduced sidewall spacers prior to forming silicide.