The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 11, 2013
Filed:
Jul. 03, 2012
Alexander Korobkov, San Jose, CA (US);
Bogdan Tutuianu, The Hills, TX (US);
Alexandre Ardelea, Austin, TX (US);
Amit Agarwal, Milpitas, CA (US);
Alexander Korobkov, San Jose, CA (US);
Bogdan Tutuianu, The Hills, TX (US);
Alexandre Ardelea, Austin, TX (US);
Amit Agarwal, Milpitas, CA (US);
Oracle International Corporation, Redwood Shores, CA (US);
Abstract
An integrated circuit clock analysis system receives a cell library of gates of the integrated circuit and generates a macro model for each of the gates, where each macro model includes at least one of a nonlinear current source model, an input parasitics model or a nonlinear capacitors model. The system then tunes the macro models and generates a simulation deck from an electrical netlist of a layout of the integrated circuit and the tuned macro models. The system then performs clock analysis simulation based on the simulation deck.