The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2013

Filed:

Dec. 18, 2009
Applicants:

Martin G. Dixon, Portland, OR (US);

Scott D. Rodgers, Hillsboro, OR (US);

Taraneh Bahrami, San Jose, CA (US);

Stephen H. Gunther, Beaverton, OR (US);

Prashant Sethi, Folsom, CA (US);

Per Hammarlund, Hillsboro, OR (US);

Inventors:

Martin G. Dixon, Portland, OR (US);

Scott D. Rodgers, Hillsboro, OR (US);

Taraneh Bahrami, San Jose, CA (US);

Stephen H. Gunther, Beaverton, OR (US);

Prashant Sethi, Folsom, CA (US);

Per Hammarlund, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2006.01); G06F 12/08 (2006.01); G06F 9/30 (2006.01);
U.S. Cl.
CPC ...
Abstract

In one embodiment, the present invention includes a processor having a core with decode logic to decode an instruction prescribing an identification of a location to be monitored and a timer value, and a timer coupled to the decode logic to perform a count with respect to the timer value. The processor may further include a power management unit coupled to the core to determine a type of a low power state based at least in part on the timer value and cause the processor to enter the low power state responsive to the determination. Other embodiments are described and claimed.


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