The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 11, 2013
Filed:
Nov. 12, 2009
Wen-yao Hsieh, Sanchong, TW;
Che-yu Chiu, Hsin-Chu, TW;
Anwei Peng, Hsin-Chu, TW;
Jian-hung Chen, Shulin, TW;
Hsueh-chen Wu, Hsin-Chu, TW;
Wen-Yao Hsieh, Sanchong, TW;
Che-Yu Chiu, Hsin-Chu, TW;
Anwei Peng, Hsin-Chu, TW;
Jian-Hung Chen, Shulin, TW;
Hsueh-Chen Wu, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
System and method for automated semiconductor manufacturing is provided. In accordance with one aspect of the present invention, a system for automated semiconductor wafer manufacturing includes a smart overlay control (SOC) database having empirical alignment data related to overlay alignment, and a simulation module communicatively coupled to the SOC database, the simulation module determining a simulated overlay alignment of a wafer on the plurality of photolithography tools in a tool bank based on the empirical alignment data stored in the SOC database. The system also includes a dispatch module communicatively coupled to the SOC database and the simulation module, the dispatch module controlling the dispatch of a wafer to one of a plurality of photolithography tools in a tool bank based at least in part on the simulated overlay alignment.