The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2013

Filed:

Dec. 16, 2010
Applicants:

Masanori Yoshida, Tokyo, JP;

Daisuke Tsuji, Tokyo, JP;

Masahito Yamato, Tokyo, JP;

Jun Sasaki, Tokyo, JP;

Kaoru Sonobe, Tokyo, JP;

Akira Ide, Tokyo, JP;

Masahiro Yamaguchi, Tokyo, JP;

Inventors:

Masanori Yoshida, Tokyo, JP;

Daisuke Tsuji, Tokyo, JP;

Masahito Yamato, Tokyo, JP;

Jun Sasaki, Tokyo, JP;

Kaoru Sonobe, Tokyo, JP;

Akira Ide, Tokyo, JP;

Masahiro Yamaguchi, Tokyo, JP;

Assignee:

Elpida Memory, Inc., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device includes a chip stacked body where a plurality of semiconductor chips are stacked, and penetration electrodes respectively formed in the semiconductor chips are electrically interconnected in stacking order of the semiconductor chips, a first support member that is disposed to face a first semiconductor chip formed in one end of the chip stacked body, and including electrodes electrically connected to the penetration electrodes of the first semiconductor chip, and a wiring board that is disposed to face a second semiconductor chip formed in an end opposed to the one end of the chip stacked body, and including external electrodes on a surface opposed to a surface facing the second semiconductor chip that is to be electrically connected to the penetration electrodes of the second semiconductor chip.


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