The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 11, 2013
Filed:
Dec. 16, 2010
Xiaolu Huang, Shanghai, CN;
Xing Wei, Shanghai, CN;
Xinhong Cheng, Shanghai, CN;
Jing Chen, Shanghai, CN;
Miao Zhang, Shanghai, CN;
Xi Wang, Shanghai, CN;
Xiaolu Huang, Shanghai, CN;
Xing Wei, Shanghai, CN;
Xinhong Cheng, Shanghai, CN;
Jing Chen, Shanghai, CN;
Miao Zhang, Shanghai, CN;
Xi Wang, Shanghai, CN;
Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Changning District Shanghai, CN;
Abstract
The present invention discloses an ESD protection structure in a SOI CMOS circuitry. The ESD protection structure includes a variety of longitudinal (vertical) PN junction structures having significantly enlarged junction areas for current flow. The resulting devices achieve increased heavy current release capability. Processes of fabricating varieties of the ESD protection longitudinal PN junction are also disclosed. Compatibility of the disclosed fabrication processes with current SOI technology reduces implementation cost and improves the integration robustness.