The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2013

Filed:

Sep. 30, 2010
Applicants:

Brian Cronquist, San Jose, CA (US);

Isreal Beinglass, Sunnyvale, CA (US);

Jan Lodewijk DE Jong, Cupertino, CA (US);

Deepak C. Sekar, San Jose, CA (US);

Zvi Or-bach, San Jose, CA (US);

Inventors:

Brian Cronquist, San Jose, CA (US);

Isreal Beinglass, Sunnyvale, CA (US);

Jan Lodewijk de Jong, Cupertino, CA (US);

Deepak C. Sekar, San Jose, CA (US);

Zvi Or-Bach, San Jose, CA (US);

Assignee:

Monolithic 3D Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 21/82 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for fabricating a device, the method including: providing a first layer including first transistors wherein the first transistors include mono-crystalline semiconductor and first alignment marks; overlaying a second semiconductor layer over the first layer, wherein the second layer includes second transistors, the second transistors include mono-crystalline semiconductor and are configured to be memory cells, at least one of the memory cells include a floating body region configured to be charged to a level indicative of a state of the memory cell, and fabricating the second transistors includes alignment to the first alignment marks.


Find Patent Forward Citations

Loading…