The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2013

Filed:

Sep. 07, 2010
Applicants:

Xinhong Cheng, Shanghai, CN;

Zhongjian Wang, Shanghai, CN;

Yuehui Yu, Shanghai, CN;

Dawei He, Shanghai, CN;

Dawei Xu, Shanghai, CN;

Chao Xia, Shanghai, CN;

Inventors:

Xinhong Cheng, Shanghai, CN;

Zhongjian Wang, Shanghai, CN;

Yuehui Yu, Shanghai, CN;

Dawei He, Shanghai, CN;

Dawei Xu, Shanghai, CN;

Chao Xia, Shanghai, CN;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/332 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention relates to a manufacturing method of SOI devices, and in particular, to a manufacturing method of SOI high-voltage power devices. The method comprises steps of: forming a first oxide layer in a section on the surface of the SOI substrate; removing the first oxide layer to form a depressed area in the corresponding section of the upper surface of the SOI substrate; forming a second oxide layer, the upper surface of which is as high as the that of the SOI substrate, in the depressed area formed in step (B); performing photoetching and doping processes to form a P-type region, an N-type region and a gate region on the thus-formed structure where the second oxide layer is formed; forming a third oxide layer by deposition on the drift region of the structure after P-type and N-type regions are formed; wherein the total thickness of the third oxide layer and the second oxide layer approximates to the thickness of the buried oxide layer in the SOI substrate; and forming metal sub-regions, which are respectively in contact with the P-type region, the N-type region and the gate region, on the structure where the third oxide layer is formed, thereby forming a high-voltage power device.


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