Nand flash memory device and method of operating same to reduce a difference between channel potentials therein

Abstract

An flash memory device includes a block of NAND cell units, each NAND cell unit in the block includes n memory cell transistors MC controlled by a plurality of n wordlines, and is connected in series between a string selection transistor SST connected to a bitline and a ground selection transistor GST. While a programming voltage Vpgm is applied to a selected wordline WL<i>, a cutoff voltage Vss is applied to a nearby unselected wordline closer to the ground selection transistor GST to isolate a first local channel Chfrom a second local channel Ch. As the location i of the selected wordline WL<i> increases close to the SST, the second channel potential Vchtends to increase excessively, causing errors. The excessive increase of Vchis prevented by modifying the voltages applied to string select lines (SSL) and/or to the bit lines (BL), or the pass voltages Vpass applied to the unselected wordlines (WL<i+1 through WL<n→), only if the selected wordline WL<i> location i is equal or greater than a predetermined (stored) location number x. If incremental step pulse programming (ISPP) is implemented, the applied voltages are modified only if the ISPP loop count j is equal or greater than a predetermined (stored) critical loop number y.