The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 04, 2013
Filed:
Jul. 04, 2012
Hsin-ming Chen, Tainan County, TW;
Shih-chen Wang, Taipei, TW;
Wen-hao Ching, Hsinchu County, TW;
Yen-hsin Lai, Taipei, TW;
Hau-yan LU, Kaohsiung, TW;
Ching-sung Yang, Hsinchu, TW;
Hsin-Ming Chen, Tainan County, TW;
Shih-Chen Wang, Taipei, TW;
Wen-Hao Ching, Hsinchu County, TW;
Yen-Hsin Lai, Taipei, TW;
Hau-Yan Lu, Kaohsiung, TW;
Ching-Sung Yang, Hsinchu, TW;
eMemory Technology Inc., Hsinchu, TW;
Abstract
An only-one-polysilicon layer non-volatile memory unit cell includes a first P-type transistor, a second P-type transistor, a N-type transistor pair, a first and second coupling capacitors is provided. The N-type transistor pair has a third transistor and a fourth transistor that are connected. The third transistor and the fourth transistor have a first floating polysilicon gate and a second floating polysilicon gate to serve as charge storage mediums, respectively. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage.