The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 04, 2013
Filed:
Feb. 09, 2011
Masashige Moritoki, Kanagawa, JP;
Takamasa Itou, Kanagawa, JP;
Takashi Ogura, Kanagawa, JP;
Tsutomu Himukai, Kanagawa, JP;
Shigeaki Shimizu, Kanagawa, JP;
Masashige Moritoki, Kanagawa, JP;
Takamasa Itou, Kanagawa, JP;
Takashi Ogura, Kanagawa, JP;
Tsutomu Himukai, Kanagawa, JP;
Shigeaki Shimizu, Kanagawa, JP;
Renesas Electronic Coporation, Kanagawa, JP;
Abstract
To provide a structure of a semiconductor device that realizes an increase in a capacitor capacitance of a memory circuit to the maximum while inhibiting an increase in a contact resistance of a logic circuit, and a manufacture method thereof. When designating the number of layers of the local interconnect layers having wiring that makes up a logic circuit area as M and designating the number of layers of the local interconnect layers having wiring that makes up the memory circuit as N (M and N are natural numbers and satisfy M>N), capacitance elements are provided over the interconnect layers comprised of (M−N) layers or (M−N+1) layers.