The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 04, 2013

Filed:

Sep. 23, 2011
Applicants:

Teak-hoon Lee, Hwaseong-si, KR;

Won-keun Kim, Hwaseong-si, KR;

Dong-hyeon Jang, Yongin-si, KR;

Ho-geon Song, Suwon-si, KR;

Sung-jun Im, Yongin-si, KR;

Inventors:

Teak-hoon Lee, Hwaseong-si, KR;

Won-keun Kim, Hwaseong-si, KR;

Dong-hyeon Jang, Yongin-si, KR;

Ho-geon Song, Suwon-si, KR;

Sung-jun Im, Yongin-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of forming a semiconductor package includes attaching a semiconductor substrate on a support substrate, wherein the semiconductor substrate includes a plurality of first semiconductor chips and a chip cutting region that separates respective ones of the semiconductor chips. A first cutting groove is formed that has a first kerf width between first and second ones of the plurality of first semiconductor chips. A plurality of second semiconductor chips is attached to the plurality of first semiconductor chips. A molding layer is formed so as to fill the first cutting groove and a second cutting groove having a second kerf width that is less than the first kerf width is formed in the molding layer so as to form individual molding layers covering one of the plurality of first semiconductor chips and one of the plurality of second semiconductor chips.


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