The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 28, 2013

Filed:

Jun. 01, 2011
Applicants:

Armagan Akar, San Jose, CA (US);

Ralph Sanchez, Amity, OR (US);

Inventors:

Armagan Akar, San Jose, CA (US);

Ralph Sanchez, Amity, OR (US);

Assignee:

Teseda Corporation, Portland, OR (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 11/00 (2006.01); G01R 31/00 (2006.01); G01R 27/28 (2006.01); G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5022 (2013.01); G06F 17/5081 (2013.01); G06F 17/5068 (2013.01); G06F 11/008 (2013.01); G01R 31/00 (2013.01); G01R 27/28 (2013.01); G01R 31/2803 (2013.01); G01R 31/281 (2013.01);
Abstract

Various embodiments related to identifying regions including physical defects in semiconductor devices are disclosed. For example, one embodiment includes receiving an electrical test mismatch reported for a scan chain; identifying a suspect logical region including a plurality of logic cones electrically connected with the scan chain; adjusting a scope of the suspect logical region by simulating data flow within the logic cones, generating simulated scan chain output based on the simulated data flow within the logic cones, and excluding at least one of the logic cones from the suspect logical region based on a comparison of the electrical test mismatch and the simulated scan chain output; after adjusting the scope of the suspect logical region, generating a candidate defect region, the candidate defect region being defined to include physical instantiations of logical cells and logical interconnections included in the suspect logical region; and displaying the candidate defect region.


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