The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 28, 2013
Filed:
Jun. 05, 2006
Tung-sun Tung, Cupertino, CA (US);
Tsair-chin Lin, Saratoga, CA (US);
Bing Zhu, Fremont, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
The invention described here is the methods of using a hardware-based functional verification system to mimic a design under test (DUT), under intended application environment and software, to record or derive the transition activities of all circuits of the DUT, then calculate the total or partial power consumption during the period of interest. The period of interest is defined by the user in terms of 'events' which are the arbitrary states of the DUT. Furthermore, the user can specify the number of sub-divisions required between events thus vary the apparent resolution of the power consumption profile.