The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 28, 2013

Filed:

Mar. 19, 2009
Applicants:

Kuan-hua Chao, Taipei County, TW;

Shiue-shin Liu, HsinChu, TW;

Jeng-horng Tsai, Kao-Hsiung, TW;

Chih-ching Chen, Miaoli County, TW;

Chuan Liu, Hsinchu, TW;

Tse-hsiang Hsu, Hsin-Chu, TW;

Inventors:

Kuan-Hua Chao, Taipei County, TW;

Shiue-Shin Liu, HsinChu, TW;

Jeng-Horng Tsai, Kao-Hsiung, TW;

Chih-Ching Chen, Miaoli County, TW;

Chuan Liu, Hsinchu, TW;

Tse-Hsiang Hsu, Hsin-Chu, TW;

Assignee:

Mediatek Inc., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01); H03L 7/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

A clock generation circuit is provided and includes a phase locked loop (PLL) and a calibrator. The PLL is arranged to receive a first clock signal and generate the output clock signal. The PLL adjusts the frequency of the output clock signal according to a control signal. The calibrator is arranged to receive the output clock signal and a second clock signal, execute a frequency calibration between the output clock signal and the second clock signal, and generate the control signal according to results of the frequency calibration.


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