The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 28, 2013
Filed:
Oct. 10, 2011
Michael R. Krames, Los Altos, CA (US);
John E. Epler, San Jose, CA (US);
Daniel A. Steigerwald, Cupertino, CA (US);
Tal Margalith, Pleasanton, CA (US);
Michael R. Krames, Los Altos, CA (US);
John E. Epler, San Jose, CA (US);
Daniel A. Steigerwald, Cupertino, CA (US);
Tal Margalith, Pleasanton, CA (US);
Koninklijke Philips Electronics N.V., Eindhoven, NL;
Philips Lumileds Lighting Company, LLC, San Jose, CA (US);
Abstract
LED layers are grown over a sapphire substrate. Individual flip chip LEDs are formed by trenching or masked ion implantation. Modules containing a plurality of LEDs are diced and mounted on a submount wafer. A submount metal pattern or a metal pattern formed on the LEDs connects the LEDs in a module in series. The growth substrate is then removed, such as by laser lift-off. A semi-insulating layer is formed, prior to or after mounting, that mechanically connects the LEDs together. The semi-insulating layer may be formed by ion implantation of a layer between the substrate and the LED layers. PEC etching of the semi-insulating layer, exposed after substrate removal, may be performed by biasing the semi-insulating layer. The submount is then diced to create LED modules containing series-connected LEDs.