The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 28, 2013
Filed:
Jun. 25, 2010
Jeffrey P. Gambino, Westford, VT (US);
Matthew D. Moon, Jeffersonville, VT (US);
William J. Murphy, North Ferrisburgh, VT (US);
James S. Nakos, Essex Junction, VT (US);
Paul W. Pastel, Essex Junction, VT (US);
Brett A. Philips, Fairfax, VT (US);
Jeffrey P. Gambino, Westford, VT (US);
Matthew D. Moon, Jeffersonville, VT (US);
William J. Murphy, North Ferrisburgh, VT (US);
James S. Nakos, Essex Junction, VT (US);
Paul W. Pastel, Essex Junction, VT (US);
Brett A. Philips, Fairfax, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Ferro-electric capacitor modules, methods of manufacture and design structures. The method of manufacturing the ferro-electric capacitor includes forming a barrier layer on an insulator layer of a CMOS structure. The method further includes forming a top plate and a bottom plate over the barrier layer. The method further includes forming a ferro-electric material between the top plate and the bottom plate. The method further includes encapsulating the barrier layer, top plate, bottom plate and ferro-electric material with an encapsulating material. The method further includes forming contacts to the top plate and bottom plate, through the encapsulating material. At least the contact to the top plate and a contact to a diffusion of the CMOS structure are in electrical connection through a common wire.