The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 21, 2013

Filed:

Jun. 30, 2006
Applicants:

Xiaojun Wang, Cary, NC (US);

Roland Ruehl, San Carlos, CA (US);

Li-ling MA, San Jose, CA (US);

Mathew Koshy, San Mateo, CA (US);

Tianhao Zhang, Raleigh, NC (US);

Udayan Gumaste, San Jose, CA (US);

Krzysztof Antoni Kozminski, San Jose, CA (US);

Haifang Liao, San Joso, CA (US);

Xinming Tu, Sunnyvalo, CA (US);

Xu Zhu, Santa Clara, CA (US);

Inventors:

Xiaojun Wang, Cary, NC (US);

Roland Ruehl, San Carlos, CA (US);

Li-Ling Ma, San Jose, CA (US);

Mathew Koshy, San Mateo, CA (US);

Tianhao Zhang, Raleigh, NC (US);

Udayan Gumaste, San Jose, CA (US);

Krzysztof Antoni Kozminski, San Jose, CA (US);

Haifang Liao, San Joso, CA (US);

Xinming Tu, Sunnyvalo, CA (US);

Xu Zhu, Santa Clara, CA (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

Disclosed is a method and system for processing the tasks performed by an IC layout processing tool in parallel. In some approaches, the IC layout is divided into a plurality of layout portions and one or more of the layout portions are processed in parallel, where geometric select operations are performed in which data for different layout portions may be shared between different processing entities. One approach includes the following actions: select phase one operation for performing initial select actions within layout portions; distributed regioning action for local regioning; distributed regioning action for global regioning and binary select; count select aggregation for count-based select operations; and select phase two operations for combining results of selecting of internal shapes and interface shapes.


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