The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 21, 2013

Filed:

Sep. 18, 2009
Applicants:

Jong Sik Paek, Seoul, KR;

IN Bae Park, Seoul, KR;

Chang Deok Lee, Uijeongbu-si, KR;

Inventors:

Jong Sik Paek, Seoul, KR;

In Bae Park, Seoul, KR;

Chang Deok Lee, Uijeongbu-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
Abstract

A stackable wafer level package and a fabricating method thereof are disclosed. In the stackable wafer level package, bond pads (or redistribution layers) are arranged on a bottom semiconductor die, and metal pillars are formed on some of the bond pads positioned around the edges of the bottom semiconductor die. A top semiconductor die is electrically connected to the other bond pads, on which the metal pillars are not formed, positioned around the center of the bottom semiconductor die through conductive bumps. The metal pillars and the top semiconductor die are encapsulated by an encapsulant. A plurality of interconnection patterns electrically connected to the metal pillars are formed on the surface of the encapsulant. Solder balls are attached to the interconnection patterns. Due to this stack structure, the wafer level package is reduced in thickness and footprint. Therefore, the wafer level package is highly suitable for mobile applications.


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