The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 14, 2013
Filed:
Nov. 09, 2011
Parijat Biswas, Bangalore, IN;
Raghurama Krishna Srigiriraju, Bangalore, IN;
Alexandru Seibulescu, San Mateo, CA (US);
Gagan Vishal Jain, Bangalore, IN;
Parijat Biswas, Bangalore, IN;
Raghurama Krishna Srigiriraju, Bangalore, IN;
Alexandru Seibulescu, San Mateo, CA (US);
Gagan Vishal Jain, Bangalore, IN;
Synopsys, Inc., Mountain View, CA (US);
Abstract
In a method for increasing coverage convergence during verification of a design for an IC, symbolic elements can be generated for the variables and the variable expressions in the hardware code of the design and a test bench. Simulation semantics can be modified and local multi-path analysis can be provided to expand symbolic property collection and symbolic element propagation. Modifying simulation semantics can include transformation of conditional statements, flattening of conditions, avoidance of short circuiting logic, and/or symbolic triggering of events. Symbolic elements are propagated through the design and the test bench during multiple simulation runs to collect symbolic properties. Coverage information from the multiple simulation runs is analyzed to identify coverage points to be targeted. For each identified coverage point, the constraints resulting from the collected symbolic properties are solved to generate directed stimuli for the design. These directed stimuli increase the coverage convergence.