The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 14, 2013
Filed:
Sep. 22, 2009
Donald R. Davis, Brighton, MI (US);
Nicolaus A. Radford, League City, TX (US);
Frank Noble Permenter, Webster, TX (US);
Michael C. Valvo, League City, TX (US);
R. Scott Askew, Houston, TX (US);
Donald R. Davis, Brighton, MI (US);
Nicolaus A. Radford, League City, TX (US);
Frank Noble Permenter, Webster, TX (US);
Michael C. Valvo, League City, TX (US);
R. Scott Askew, Houston, TX (US);
GM Global Technology Operations LLC, Detroit, MI (US);
The United States of America as represented by the Administrator of the National Aeronautics and Space Administration, Washington, DC (US);
Oceaneeering Space Systems, Webster, TX (US);
Abstract
A control system for achieving high-speed torque for a joint of a robot includes a printed circuit board assembly (PCBA) having a collocated joint processor and high-speed communication bus. The PCBA may also include a power inverter module (PIM) and local sensor conditioning electronics (SCE) for processing sensor data from one or more motor position sensors. Torque control of a motor of the joint is provided via the PCBA as a high-speed torque loop. Each joint processor may be embedded within or collocated with the robotic joint being controlled. Collocation of the joint processor, PIM, and high-speed bus may increase noise immunity of the control system, and the localized processing of sensor data from the joint motor at the joint level may minimize bus cabling to and from each control node. The joint processor may include a field programmable gate array (FPGA).