The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8441832 B1

PDF
Full Text
Expired
Date of Patent:
May. 14, 2013

Filed:

Jul. 22, 2011
Applicant:

Yasushi Matsubara, Tokyo, JP;

Inventor:

Yasushi Matsubara, Tokyo, JP;

Assignee:

Elpida Memory, Inc., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

For example, to include plural data input/output terminals and a strobe terminal that are electrically connected in common by a test probe, a command address terminal that is connected to a test probe, and an output control circuit that performs a selecting operation of data output circuits based on a signal that is supplied to the command address terminal. According to the present invention, it is possible to perform a test that uses non-compressed actual data while allocating plural data input/output terminals to one determination circuit within a tester. With this configuration, it is possible to test a large number of semiconductor devices in parallel by using a limited number of determination circuits within the tester.


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Matsubara, Yasushi. (2013). Semiconductor device and test method thereof (U.S. Patent No. 8441832). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8441832

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