The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 14, 2013
Filed:
Oct. 01, 2010
Yoshitaka Sasaki, Santa Clara, CA (US);
Hiroyuki Ito, Milpitas, CA (US);
Hiroshi Ikejima, Hong Kong, CN;
Atsushi Iijima, Hong Kong, CN;
Yoshitaka Sasaki, Santa Clara, CA (US);
Hiroyuki Ito, Milpitas, CA (US);
Hiroshi Ikejima, Hong Kong, CN;
Atsushi Iijima, Hong Kong, CN;
Headway Technologies, Inc., Milpitas, CA (US);
Sae Magnetics (H.K.) Ltd., Hong Kong, CN;
Abstract
A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes: a main part including first and second layer portions; and a plurality of first and second terminals that are disposed on the top and bottom surfaces of the main part, respectively, and are electrically connected to the plurality of wires. The first and second terminals are formed by using electrodes of the first and second layer portions. The layered chip package is manufactured by fabricating a layered substructure by stacking two substructures each of which includes an array of a plurality of preliminary layer portions, and then cutting the layered substructure. The layered substructure includes a plurality of preliminary wires that are disposed between two adjacent pre-separation main bodies and are to become the plurality of wires.