The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 07, 2013

Filed:

Feb. 06, 2012
Applicants:

Igor Arsovski, Williston, VT (US);

Matthew W. Deming, Essex Junction, VT (US);

Darryl R. Hill, Colchester, VT (US);

Harold Pilo, Underhill, NY (US);

Reid A. Wistort, Westford, VT (US);

Inventors:

Igor Arsovski, Williston, VT (US);

Matthew W. Deming, Essex Junction, VT (US);

Darryl R. Hill, Colchester, VT (US);

Harold Pilo, Underhill, NY (US);

Reid A. Wistort, Westford, VT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/08 (2006.01);
U.S. Cl.
CPC ...
Abstract

A dual word-line level shifter circuit and associated SRAM. A circuit is disclosed that includes a first transistor gated by a data input at the lower voltage, and a second transistor gated by a restore input at the higher voltage, wherein the first and second transistors are coupled along a series path to a source at the higher voltage; a control node along the series path; an output node coupled to the control node via a first pair of parallel transistors; and a feedback circuit having a second pair of parallel transistors and a feedback transistor, wherein the feedback transistor couples the second pair of parallel transistors to the control node and is gated by the output node.


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