The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 07, 2013
Filed:
Jul. 01, 2011
David W. Mendel, Sunnyvale, CA (US);
Triet M. Nguyen, San Jose, CA (US);
LU Zhou, Santa Clara, CA (US);
Gary Lai, Palo Alto, CA (US);
David W. Mendel, Sunnyvale, CA (US);
Triet M. Nguyen, San Jose, CA (US);
Lu Zhou, Santa Clara, CA (US);
Gary Lai, Palo Alto, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
A programmable logic device includes logic blocks such as a logic array blocks (LAB) that can be configured as a random access memory (RAM) or as a lookup table (LUT). A mode flag is provided to indicate the mode of operation of configuration logic such as a configuration RAM (CRAM) used during partial reconfiguration of a logic block. If the mode flag indicates a design state, the configuration logic associated with the logic block is included in data verification and correction processes. If the mode flag indicates a user defined state, the configuration logic associated with the logic block is excluded from data verification and correction processes. Thus, exclusion and inclusion of portions of a region of configuration logic from data verification and correction processes allow a region of configuration logic to store both a design state and a user defined state without causing deleterious effects.