The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 30, 2013
Filed:
Mar. 20, 2012
Der-min Yuan, New Taipei, TW;
Kuang-fu Teng, Ping-Tung County, TW;
Chun Shiah, Hsinchu, TW;
Feng-chia Chang, New Taipei, TW;
Der-Min Yuan, New Taipei, TW;
Kuang-Fu Teng, Ping-Tung County, TW;
Chun Shiah, Hsinchu, TW;
Feng-Chia Chang, New Taipei, TW;
Etron Technology, Inc., Hsinchu, TW;
Abstract
A delay lock loop system includes a timing controller, an OR gate, an input buffer, a pulse generator, and a delay lock loop. The timing controller is used for outputting an external enable signal periodically while a power saving signal is at a logic-low voltage, and being disabled according to a logic-high voltage of the power saving signal. The pulse generator is used for generating a pulse according to the positive edge of the power saving signal. The OR gate is coupled to the timing controller for receiving the power saving signal, the pulse, and the external enable signal, and outputting an enable signal according to the power saving signal and the external enable signal. The delay lock loop is coupled to the OR gate and the input buffer for enabling the delay lock loop again according to the enable signal.