The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8432186 B1

PDF
Full Text
Expired
Date of Patent:
Apr. 30, 2013

Filed:

May. 31, 2012
Applicants:

Koichiro Zaitsu, Kawasaki, JP;

Kosuke Tatsumura, Kawasaki, JP;

Mari Matsumoto, Yokohama, JP;

Shinichi Yasuda, Tokyo, JP;

Masato Oda, Yokohama, JP;

Haruka Kusai, Yokohama, JP;

Kiwamu Sakuma, Yokohama, JP;

Inventors:

Koichiro Zaitsu, Kawasaki, JP;

Kosuke Tatsumura, Kawasaki, JP;

Mari Matsumoto, Yokohama, JP;

Shinichi Yasuda, Tokyo, JP;

Masato Oda, Yokohama, JP;

Haruka Kusai, Yokohama, JP;

Kiwamu Sakuma, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/173 (2006.01);
U.S. Cl.
CPC ...
Abstract

One embodiment provides a programmable logic switch in which a first nonvolatile memory and a second nonvolatile memory are formed in the same well, and in which to change the first nonvolatile memory from an erased state to a written state and leave the second nonvolatile memory being in the erased state, a first write voltage is applied to a first line connected with gate electrodes of the first and second nonvolatile memories, a second write voltage is applied to a second line connected to a source in the first nonvolatile memory, and a third write voltage lower than the second write voltage is applied to a fourth line connected to a source of the second nonvolatile memory.


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