Semiconductor memory device having vertical transistor and buried bit line and method for fabricating the same

Abstract

A semiconductor memory device includes an active region protruding upward from a substrate, wherein the active region is arranged next to a trench on the substrate, a first impurity region formed at an upper portion of the active region, a second impurity region formed at a lower portion of the active region, a gate dielectric layer formed along a side of the active region between the first impurity region and the second impurity region, a gate electrode layer formed on the gate dielectric layer, a buried bit line formed at a lower portion of the trench, and a polysilicon layer formed over the buried bit line, wherein the polysilicon layer electrically connects the buried bit line with the second impurity region.