The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 30, 2013
Filed:
Aug. 09, 2012
Joel P. DE Souza, Putnam Valley, NY (US);
Keith E. Fogel, Hopewell Junction, NY (US);
Edward W. Kiewra, Verbank, NY (US);
Steven J. Koester, Ossining, NY (US);
Christopher C. Parks, Poughkeepsie, NY (US);
Devendra K. Sadana, Pleasantville, NY (US);
Shahab Siddiqui, White Plains, NY (US);
Joel P. de Souza, Putnam Valley, NY (US);
Keith E. Fogel, Hopewell Junction, NY (US);
Edward W. Kiewra, Verbank, NY (US);
Steven J. Koester, Ossining, NY (US);
Christopher C. Parks, Poughkeepsie, NY (US);
Devendra K. Sadana, Pleasantville, NY (US);
Shahab Siddiqui, White Plains, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method of preventing surface decomposition of a III-V compound semiconductor is provided. The method includes forming a silicon film having a thickness from 10 Å to 400 Å on a surface of an III-V compound semiconductor. After forming the silicon film onto the surface of the III-V compound semiconductor, a high performance semiconductor device including, for example, a MOSFET, can be formed on the capped/passivated III-V compound semiconductor. During the MOSFET fabrication, a high k dielectric can be formed on the capped/passivated III-V compound semiconductor and thereafter, activated source and drain regions can be formed into the III-V compound semiconductor.