The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 23, 2013
Filed:
Jul. 18, 2011
Yoshitaka Sasaki, Santa Clara, CA (US);
Hiroyuki Ito, Milpitas, CA (US);
Hiroshi Ikejima, Hong Kong, CN;
Atsushi Iijima, Hong Kong, CN;
Yoshitaka Sasaki, Santa Clara, CA (US);
Hiroyuki Ito, Milpitas, CA (US);
Hiroshi Ikejima, Hong Kong, CN;
Atsushi Iijima, Hong Kong, CN;
Headway Technologies, Inc., Milpitas, CA (US);
SAE Magnetics (H.K.) Ltd., Hong Kong, CN;
Abstract
A composite layered chip package includes a plurality of subpackages stacked on each other. Each subpackage includes a main body and wiring. The main body includes a main part including a plurality of layer portions, and further includes first terminals and second terminals that are disposed on top and bottom surfaces of the main part, respectively. The wiring is electrically connected to the first and second terminals. The number of the plurality of layer portions included in the main part is the same for all the plurality of subpackages, and the plurality of layer portions in every subpackage include at least one first-type layer portion. In each of at least two of the subpackages, the plurality of layer portions further include at least one second-type layer portion. The first-type layer portion includes a semiconductor chip connected to the wiring, whereas the second-type layer portion includes a semiconductor chip not connected to the wiring.