The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 23, 2013

Filed:

Sep. 19, 2011
Applicants:

Kyu-hee Han, Hwaseong-si, KR;

Sang-hoon Ahn, Hwaseong-si, KR;

Jang-hee Lee, Yongin-si, KR;

Jong-min Beak, Suwon-si, KR;

Kyoung-hee Kim, Incheon, KR;

Byung-iyul Park, Seoul, KR;

Byung-hee Kim, Seoul, KR;

Inventors:

Kyu-hee Han, Hwaseong-si, KR;

Sang-hoon Ahn, Hwaseong-si, KR;

Jang-hee Lee, Yongin-si, KR;

Jong-min Beak, Suwon-si, KR;

Kyoung-hee Kim, Incheon, KR;

Byung-Iyul Park, Seoul, KR;

Byung-hee Kim, Seoul, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 21/44 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of forming through silicon vias (TSVs) includes forming a primary via hole in a semiconductor substrate, depositing low-k dielectric material in the primary via hole, forming a secondary via hole by etching the low-k dielectric in the primary via hole, in such a manner that a via insulating layer and an inter metal dielectric layer of the low-k dielectric layer are simultaneously formed. The via insulating layer is formed of the low-k dielectric material on sidewalls and a bottom surface of the substrate which delimit the primary via hole and the inter metal dielectric layer is formed on an upper surface of the substrate. Then a metal layer is formed on the substrate including in the secondary via hole, and the metal layer is selectively removed from an upper surface of the semiconductor substrate.


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