The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 16, 2013
Filed:
Feb. 22, 2010
Paul C. Foster, Scotts Valley, CA (US);
Tina M. Najibi, San Jose, CA (US);
Walter E. Hartong, Isen, DE;
T. Martin O'leary, San Jose, CA (US);
Paul C. Foster, Scotts Valley, CA (US);
Tina M. Najibi, San Jose, CA (US);
Walter E. Hartong, Isen, DE;
T. Martin O'Leary, San Jose, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
An electronic design automation (EDA) tool to validate representations of a design is disclosed. Reference and compared representations of the design are intended to respond to stimulus in the same way, but at different levels of abstraction. The reference and compared representations are simulated, at some point, to each generate waveform signals and measured results. Simulation can be with the same tool or different tools. The same or different testbench can be used on the reference and compared representations in the simulation. A design representation validation function compares the two sets of generated waveform signals and compares the two sets of measured results to identify any violations. The measured results and/or waveform signals could be loaded from previous simulations and just validated within the validation tool. Loaded simulations could be for the reference representation with just simulation of the compared representation by the validation tool, or for both with no simulations run by the validation tool. Through an optional design representation validation interface, the violations are identified and are linked to interfaces that detail the violations in greater detail, for example, to aid in debugging why the reference and compared representations are not equivalent.