The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 16, 2013
Filed:
Jan. 11, 2011
Pamela S. Gillis, Jericho, VT (US);
David E. Lackey, Jericho, VT (US);
Steven F. Oakland, Colchester, VT (US);
Jeffery H. Oppold, Richmond, VT (US);
Pamela S. Gillis, Jericho, VT (US);
David E. Lackey, Jericho, VT (US);
Steven F. Oakland, Colchester, VT (US);
Jeffery H. Oppold, Richmond, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A scannable register array structure includes a plurality of individual latches, each configured to hold one bit of array data in a normal mode of operation. The plurality of individual latches operate in scannable latch pairs in a test mode of operation, with first latches of the scannable latch pairs comprising L1 latches and second latches of the scannable latch pairs comprising L2 latches. A test clock signal generates a first clock pulse signal, A, for the L1 latches and a second clock pulse signal, B, for the L2 latches. The L2 latches are further configured to selectively receive L1 data therein upon a separate activation of the B clock signal, independent of the test clock signal, such that a scan out operation of the individual latches results in observation of L1 latch data.