The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 16, 2013

Filed:

Jun. 03, 2010
Applicants:

Shunichi Saito, Tokyo, JP;

Toshio Sugano, Tokyo, JP;

Atsushi Hiraishi, Tokyo, JP;

Fumiyuki Osanai, Tokyo, JP;

Masayuki Nakamura, Tokyo, JP;

Hiroki Fujisawa, Tokyo, JP;

Inventors:

Shunichi Saito, Tokyo, JP;

Toshio Sugano, Tokyo, JP;

Atsushi Hiraishi, Tokyo, JP;

Fumiyuki Osanai, Tokyo, JP;

Masayuki Nakamura, Tokyo, JP;

Hiroki Fujisawa, Tokyo, JP;

Assignee:

Elpida Memory, Inc., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

A memory module includes a plurality of memory chips, a plurality of data register buffers, and a command/address/control register buffer mounted on a module PCB. The data register buffers perform data transfers with the memory chips. The command/address/control register buffer performs buffering of a command/address/control signal and generates a control signal. The buffered command/address/control signal is supplied to the memory chips, and the control signal is supplied to the data register buffers. According to the present invention, because line lengths between the data register buffers and the memory chips are shortened, it is possible to realize a considerably high data transfer rate.


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