The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 16, 2013
Filed:
Jun. 24, 2010
Yoshitaka Sasaki, Milpitas, CA (US);
Hiroyuki Ito, Milpitas, CA (US);
Hiroshi Ikejima, Hong Kong, CN;
Atsushi Iijima, Hong Kong, CN;
Yoshitaka Sasaki, Milpitas, CA (US);
Hiroyuki Ito, Milpitas, CA (US);
Hiroshi Ikejima, Hong Kong, CN;
Atsushi Iijima, Hong Kong, CN;
Headway Technologies, Inc., Milpitas, CA (US);
SAE Magnetics (H.K.) Ltd., Hong Kong, CN;
Abstract
A layered chip package includes a main body, and wiring disposed on a side surface of the main body. The main body includes: a main part including a plurality of layer portions stacked; a plurality of first terminals disposed on the top surface of the main part and connected to the wiring; and a plurality of second terminals disposed on the bottom surface of the main part and connected to the wiring. The plurality of layer portions include a first-type layer portion and a second-type layer portion. The first-type layer portion includes a conforming semiconductor chip, and a plurality of first-type electrodes that are connected to the semiconductor chip and the wiring. The second-type layer portion includes a defective semiconductor chip, and a plurality of second-type electrodes that are connected to the wiring and not to the semiconductor chip.